Among well-known semiconductor packages, leadframe-based semiconductor packages have been widely implemented by using leadframes as chip carriers. Advanced leadframes have a plurality of metal leads not only for electrical connections but also for carrying chips by extending metal leads onto chip surfaces to eliminate or shrink the dimension of the die pad of a conventional leadframe. The leadframes with shrunk die pads or without die pads for leadframe-based semiconductor packages can be classified into two different package types, Lead-On-Chip (LOC) and Chip-On-Lead (COL), where “Lead-On-Chip” means to attach the leads to the active surface of a chip and “Chip-On-Lead” means to attach the back surface of a chip to the middle sections of the leads. However, no matter it is an LOC package or a COL package, it is very common that chips are attached to the leads of a leadframe by die-attaching tapes and are electrically connected to the leads of a leadframe by bonding wires to meet the requirements of smaller dimensions and lower cost for high-speed applications. Since the chips are attached to the leads of a leadframe by die-attaching tapes, therefore, the stresses exerted on the leads of a leadframe will pass along to other parts of the package and will accumulate at certain locations leading to reliability issues.
As shown in FIG. 1, a conventional leadframe-based semiconductor package 100 is an LOC-type package, primarily comprising a chip 110, a plurality of leads 120 of a leadframe, a multi-layer tape 130, a plurality of bonding wires 140, and an encapsulant 150. The chip 110 has an active surface 111 and a corresponding back surface 112 where a plurality of bonding pads 113 are disposed at the center of the active surface 111. The leads 120 are made of metals. Each lead 120 has an internal lead 121 and an external lead 122 where the internal lead 121 has a first surface 123 away from the chip 110 and a second surface 124 adjacent to the chip 110. The internal leads 121 are extended to the active surface 111 toward the bonding pads 113. The external leads 122 are extended from the sides of the encapsulant 150 which are bent and formed as external terminals for external electrical connections. The leads 120 are attached to the active surface 111 of the chip 110 by the multi-layer tape 130. The bonding pads 113 are electrically connected to the internal leads 121 by the bonding wires 140. The encapsulant 150 is formed by transfer molding to encapsulate the chip 110, the internal leads 121, and the bonding wires 140.
FIG. 2 is the partially enlarged cross-sectional view of a conventional leadframe-based semiconductor package 100 cross-sectioned along a plurality of internal leads 121 of the leads 120 of a leadframe. The multi-layer tape 130 comprises a dielectric core layer 131, a first adhesive layer 132 for die-attaching, and a second adhesive layer 133. Firstly, the second adhesive layer 133 is attached to the internal leads 121 by first bonding where the dielectric layer 131 has no adhesions so that the multi-layer tape 130 is disposed beneath the internal leads 121. During the packaging processes, the second adhesive layer 133 is softened by heating where a downward pressure will exert on the internal leads 121 to make the first adhesive layer 132 adhere to the chip 110. But this re-bonding operation also pushes the internal leads 121 to be more embedded in the second adhesive layer 133 until the second surfaces 124 of the internal leads 121 directly contact the dielectric core layer 131 leading to poor or no adhesions between the second surface 124 of the internal leads 121 and the dielectric core layer 131. Moreover, the adhesions between the internal leads 121 and the multi-layer tapes 130 are only relied on the bonding interface between the second adhesive layer 133 and two corresponding sidewalls of the internal leads 121 leading to easily shifting of internal leads and delamination.
Another issue encountered during packaging processes of a conventional leadframe-based package is the downward pressure exerts on the internal leads 121 is too small where the internal leads 121 do not sink into the second adhesive layer 133 so that the adhesions between the internal leads 121 and the second adhesive layer 133 are totally counted on the planar adhesions on the second surface 124 of the internal leads 121 causing lead shifting leading to electrical short. Especially, the internal leads 121 disposed adjacent to the corners of the package 100 will experience maximum stresses, therefore, if the adhesions between the internal leads 121 and the multi-layer tapes 130 are poor, lead peeling or delamination will occur at the interfaces between the internal leads 121 and the multi-layer tapes 130 leading to poor bond ability of bonding wires. Furthermore, the adhesions between the chip 110 and the first adhesive layer 132 are also poor because of the weak re-bonding pressure.